Intel's 18A Just Killed the ARM Efficiency Myth

A $699 Dell XPS 13 running Fedora just did something no x86 machine has done before: it out-sipped Apple Silicon. In Jeff Geerling's HPL Linpack testing, the XPS 13's Intel Core 5 320 — a low-end "Wildcat Lake" part — pushed 127.91 Gflops at 20.6 watts, or 6.21 Gflops per watt. Apple's new $599 MacBook Neo, built around the A18 Pro, managed 5.38. That lands the Dell in the top ten of Geerling's community-run efficiency leaderboard, behind only the M4 Mac mini among consumer machines. Before this, no x86 system on that chart had even cracked 3 Gflops per watt.

One benchmark on one cheap laptop shouldn't reshape anyone's worldview. But this one kills an argument that's been zombie-walking through hardware discussions for fifteen years.

The ISA was never the problem

The folk theory — ARM is "inherently" efficient because of its lean instruction set, x86 drags around decoder baggage — has been on shaky ground since researchers started measuring it seriously in the early 2010s. Decode overhead is a rounding error on a modern wide out-of-order core. What actually determined the efficiency gap was everything else: process node, design targets, idle-state engineering, and how aggressively the memory subsystem was integrated.

Apple's M1 moment in 2020 looked like an ARM victory, but it was really a TSMC-5nm-plus-ruthless-design victory. Intel tacitly conceded the point in 2024 when it built Lunar Lake — its previous best efficiency showing — on TSMC's N3B rather than its own fabs. That chip proved Intel's architects could design for efficiency; it also proved Intel's foundry couldn't yet deliver it.

Wildcat Lake is different in the way that matters strategically: it's built on Intel 18A, in Intel's own fabs, with RibbonFET gate-all-around transistors and PowerVia backside power delivery. The Core 5 320 is a deliberately modest design — two Cougar Cove P-cores, four Darkmont E-cores, a two-core Xe3 iGPU, topping out at 4.6 GHz. And that modest design on 18A roughly doubled the best FP64 efficiency any x86 chip had ever posted on Geerling's chart. The gains are coming from the node and the low-power plumbing, not from a hero core. That's exactly what Intel needed to demonstrate, because nodes scale across a product line; hero cores don't.

Read the fine print before rewriting your roadmap

The honest caveats, because the headline invites overreach. First, HPL is FP64 dense linear algebra — a wonderful, portable yardstick and almost nobody's production workload. Second, the comparison is friendly to Intel: the MacBook Neo is a fanless $599 machine repurposing a 2024 iPhone chip, not Apple's efficiency frontier. The M4 Mac mini still leads at 7.57 Gflops per watt, and Apple hasn't shipped its M5-generation answer at this price point yet. Third, efficiency was measured near this chip's happy point on the power curve; absolute throughput is a little over 120 Gflops, where M3 and M4 Macs push toward 1.2 teraflops. Wildcat Lake matches Apple's ratio, not Apple's performance.

What survives the caveats is still substantial. Geerling measured 0.6 W at idle with the display off and about 4 W with it on — territory x86 laptops simply didn't occupy. Geekbench on Fedora 44 came in around 2,488 single / 8,093 multi, respectable for a six-core budget part, and everything worked under mainline Linux without vendor-tree archaeology.

Where this actually bites: the edge, not the datacenter

The framing "Intel beats ARM" points at the wrong battlefield. Wildcat Lake says nothing yet about Graviton or Ampere in the datacenter — those are 96-plus-core server designs, and Intel's 18A server story (Diamond Rapids and successors) is still unproven. If you're running fleets on AWS Graviton, nothing changed this week.

Where the calculus shifts immediately is small-box compute: edge nodes, retail and industrial gateways, homelab clusters, on-prem appliances. The pitch for ARM SBCs and mini PCs in those roles was always "sips power, tolerable performance, put up with the software friction." A Wildcat Lake box inverts that. You get sub-watt idle and phone-class load efficiency with none of the ARM tax: no cross-compilation, no waiting on vendor kernel patches, no checking whether your container images publish arm64 variants, no U-Boot spelunking. Every x86 binary from the last two decades just runs. Beelink and the usual mini-PC vendors are already shipping 18A boxes, and Intel is explicitly aiming the platform at low-cost laptops and embedded systems.

Temper the AI-inference angle specifically, though. The Core 5 320's NPU is specced in the mid-teens of TOPS and the iGPU is two Xe3 cores — fine for background transcription, embeddings, or a small quantized model at the edge, not a substitute for real inference hardware. The per-watt story matters here as a signal of what 18A does for Intel's bigger silicon, not because this SKU will serve your models.

The verdict

This is a genuine shift, not hype — but the shift is "the x86 efficiency penalty was a fab problem, and Intel's fab problem looks fixed," not "Intel beats ARM." One well-corroborated data point from an independent tester, on Intel's first high-volume 18A part, at the unglamorous bottom of the lineup, is precisely the kind of evidence that's hard to fake with marketing. Apple still owns the efficiency crown when it ships current-generation M-series silicon at full effort, and ARM's server incumbents are untouched for now.

But the default assumption — that power-constrained means ARM — is dead as of this benchmark. If Panther Lake and Intel's server parts show the same 18A character, the interesting question for 2027 isn't whether x86 can match ARM per watt. It's whether ARM licensees on TSMC can keep justifying the software friction once they can't win on the power bill.